1. Field of the Invention
This invention relates to a video memory for use with a video tape recorder, a television receiver or the like to process a video signal.
2. Description of the Prior Art
A video memory for processing a video signal as previously proposed is shown in FIG. 1.
Referring to FIG. 1, a video signal is applied to an input terminal 1 and this video signal is then supplied to a multiplier 2 in which it is multiplied by a coefficient K (K&lt;1). The output signal from the multiplier 2 is supplied through an adder 3 to a frame delay circuit 4 in which it is delayed by a delay time of one frame period. The output signal from the frame delay circuit 4 is supplied to a multiplier 5 in which it is multiplied by a coefficient 1-K. The output signal from the multiplier 5 is supplied to the adder 3 in which it is added with the output signal from the multiplier 2. The output signal from the frame delay circuit 4 is supplied through a first-in-first-out memory (hereinafter simply referred to as FIFO) circuit 6 to an output terminal 7.
The multiplier 2, the adder 3, the frame delay circuit 4 and the multiplier 5 constitute a kind of low pass filter having a time constant K and which constitutes a noise reducer circuit for reducing a noise component contained in the video signal. The frame delay circuit 4 may be formed of a generally available dynamic random access memory (hereinafter simply referred to as a DRAM). Since the frame delay circuit 4 operates at low speed, a serial-parallel converter and a parallel-serial converter are connected to the input and output sides of this frame delay circuit 4 though not shown.
The FIFO circuit 6 is used as a time base corrector. According to this FIFO circuit 6, the data supplied thereto is written in its memory by a write clock synchronized with an incoming video signal and in which the written data is read out from the memory by a reference read clock asynchronous to the write clock and which is developed externally. Also, since this FIFO circuit 6 operates at low speed, a serial-parallel converter and a parallel-serial converter are connected to the input and output sides thereof though not shown.
When the known video memory is constructed as shown in FIG. 1, a plurality of memories are used to reduce the noise component and to correct the time base error thereby to improve the quality of a picture. In other words, since the frame memory is used to reduce the noise component and the FIFO memory is used to correct the time base error, the known video memory is complicated in circuit arrangement. Further, these memories require control circuits for their operation. This makes the peripheral circuit complicated, the system large in size and causes several defects from a cost standpoint and from a design standpoint.
A frequency converter circuit is used in the above mentioned video memory apparatus. This frequency converter is suitable for a video memory apparatus. The known frequency converter circuit (frame synchronizer) for converting a frequency is constructed, as for example, shown in FIG. 2.
Referring to FIG. 2, there are shown a plurality of frame memories (or field memories) 1a and 2a. These frame memories 1 and 2a are supplied with data of the upper 4 bits and data of the lower 4 bits of a composite color video signal of 8 bits. That is, the frame memories 1a and 2a are each adapted to write data of 4 bits supplied thereto in turn in response to a write clock signal CKW and to read the same in response to a read clock signal CKR. At that time, the write clock signal CKW and the read clock signal CKR are not synchronized with each other so that the frame memories 1a and 2a generate output signals of frequencies different from those of the input signals, or output signals which are frequency-converted.
When "crossing" occurs between a write address signal and a read address signal used in the frame memories 1a and 2a as will be described later, this crossing is detected by a crossing detecting circuit 3a. Then, on the basis of the detected results from the crossing detecting circuit 3a, a chroma inverter 4a, to which the data read out from the memories 1a and 2a are supplied, shifts the phase of a subcarrier by 180.degree. and supplies a video signal with correct color reproduction to an output terminal 5A.
The frame memories 1a and 2a may be each constructed, for example as shown in FIG. 3. As shown in FIG. 3, a video signal applied to an input terminal 10 is sequentially written in a serial access memory (hereinafter referred to as SAM) 11 of a line unit in response to the write clock CKW. The data written in the SAM 11 is transferred to a DRAM (dynamic random access memory) 12 and written in the DRAM 12 at its predetermined position designated by an address signal from a write address circuit 13 formed of a counter and which is supplied with a clock signal CLK.
The data written in the predetermined position of the DRAM 12 is designated by an address signal from a read address circuit 14, which is formed of a counter and supplied with the clock signal CLK, read out therefrom and transferred to and written in a SAM 16. The data transferred to the SAM 16 is shifted bit by bit each time the read clock signal CKR is supplied to the SAM 16 and then supplied to an output terminal 17. The SAMs 11 and 16 are of the same storage capacity and the clock signals CKW and CKR are not synchronized with each other.
With the circuit arrangement shown in FIG. 2, since the input and the output of each of the frame memories 1a and 2a are not synchronized with each other, the write address signal from the address circuit 13 and the read address signal from the address circuit 14 cross each other at times. When they cross each other, data is exchanged from the present field to the immediately-preceding field. This will be explained more fully with reference to FIG. 4. In FIG. 4, a solid line assumes a transition of the write address signal with respect to time and a dashed line assumes a transition of the read address signal with respect to time. Also, let it be assumed that the read address signal is higher than the write address signal in frequency (with a shorter cycle). Then, if the write address signal and the read address signal do not cross, the field information of an n-th field would be read out from t.sub.1 to t.sub.2 ; the field information of an (n+1)-th field would be read out from the time t.sub.2 to t.sub.4 ; the field information of an (n+2)-th field would be read out from t.sub.4 to t.sub.5 ; and the field information of an (n+3)-th field would be read out from time t.sub.5 to t.sub.6. However, when the read address signal crosses the write address signal at time t.sub.3, the field information of the (n+1)-th field, namely, the field information at the present field is read out from time t.sub.2 to t.sub.3 but the field information of the n-th field, or field information before the preceding field information is read out from time point t.sub.3 to t.sub.4 as shown in FIG. 4. Similarly, the field information of one field before such as the field information of the (n+1)-th field is read out from the time t.sub.4 to t.sub.5 and the field information of the (n+2)-th field is read out from time t.sub.5 to t.sub.6 and so on.
In the circuit arrangement in which the frame memory 1a for the higher 4 bits and the frame memory 2a for the lower 4 bits are used as shown in FIG. 2, the above mentioned crossing does not cause any trouble, if it occurs both in the frame memories 1a and 2a simultaneously. However, it causes a serious trouble if the crossing does not occur at the same time between the frame memories 1and 2a due to the scattering of delay in the memories 1a and 2a. That is, at that time the field information and the field information of one field before are mixed between the upper 4 bits and the lower 4 bits. As a result, this exerts a fatal bad influence upon the picture.